This invention relates generally to a CMOS device and to a method for the fabrication of CMOS devices, and more specifically to a silicided CMOS device and to a process for its fabrication.
In the fabrication of many CMOS integrated circuits, polycrystalline or amorphous silicon is used both as a gate electrode and as a material for interconnecting various devices which are combined to implement the integrated circuit function. The polycrystalline silicon is heavily doped with conductivity determining impurities to increase the conductivity of the material and thereby to increase the speed of the circuit, to increase the transconductance of individual transistors, and to otherwise improve the circuit performance. Thin, heavily doped silicon layers, however, still have an appreciable resistivity which must be overcome to achieve optimum circuit speed. The resistivity of the thin silicon layer can be reduced to an acceptable level by forming a silicide layer on the silicon. A silicide layer at the point of contact to the semiconductor substrate can also improve the contact resistance between a substrate region and an interconnecting means. Providing a silicide layer on the thin layer of silicon, however, can introduce an unacceptable shift in an important device parameter. To understand this it must be noted that the threshold voltage of a silicon gate MOS transistor is dependant upon the impurity doping level in the silicon gate electrode because this doping level determines the work function between the gate electrode and the underlaying substrate. It is usual to dope the gate electrode of P channel MOS transistors with a P type dopant and the gate electrode of N channel transistors with an N type dopant. The gate electrodes of N channel and P channel transistors are often connected together by a patterned portion of the same thin silicon layer from which the gate electrodes are fabricated. This interconnection between gate electrodes of different devices is a normal part of the interconnection of devices to implement the intended circuit function. It has been found that the diffusion of dopant impurities is significantly accelerated in silicon layers which have been silicided. As a result, the dopant impurities diffuse rapidly through the silicided silicon layers with the deleterious result that the gate electrodes of P channel transistors become doped with the rapidly migrating N type dopant impurities and vice versa for N channel transistors. This changes the threshold voltage, for example, of the P channel transistors to an unacceptably high value.
A need therefore existed for a method to lower the resistivity of silicon gate electrodes and interconnections and to provide silicided contacts to source and drain regions without causing undesirable shifts in threshold voltage.
It is therefore an object of this invention to provide an improved process for the fabrication of silicon gate CMOS devices.
It is another object of this invention to provide an improved process for the fabrication of silicon gate CMOS devices having low resistivity gate electrodes and interconnections and having silicided contacts to source and drain regions.
It is yet another object of this invention to provide improved silicon gate CMOS devices.
It is a still further object of this invention to provide improved silicon gate CMOS devices having highly conductive gate electrodes and interconnections and having silicided contacts to source and drain regions.